Exemplary embodiments relate to a semiconductor memory device and a method of operating the same.
A semiconductor memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings corresponding to the respective bit lines.
The row decoder, coupled to a string select line, word lines, and a common source line, is disposed on one side of the memory cell array. The page buffer coupled to the plurality of bit lines is disposed on the other side of the memory cell array.
In order to further improve the degree of integration of the semiconductor memory devices, active research is being done on a multi-bit cell capable of storing multiple bits in one memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing single bit data is called a single level cell (SLC).
In the semiconductor memory device, the page buffer senses data or stores data as required. The page buffer includes a latch circuit for latching data to be programmed into memory cells or reading data programmed into memory cells and temporarily storing the read data. The number of latches included in the page buffer is increased because the memory cell is changed into the multi-level cell.